1. Field of the Invention
The present invention relates to a timing signal generating circuit, a semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied and a signal transmission system and, more particularly, to a timing signal generating circuit aimed at increasing the speed of signal transmission between LSI (Large Scale Integration Circuit) chips or between a plurality of devices or circuit blocks within one chip.
2. Description of the Related Art
Recently, the performance of components used in computers and other information processing apparatuses has improved rapidly; in particular, the performance of dynamic random access memories (DRAMs) and processors has improved dramatically year by year.
Namely, processor performance has increased dramatically in terms of speed, whereas DRAM performance improvements have been dramatic primarily in terms of storage capacity. However, the improvement in DRAM speed has not been so dramatic as the increase in storage capacity, as a result of which a gap between the speed of DRAMs and that of processors has widened and, in recent years, this speed gap has been becoming a bottleneck in boosting computer performance.
Further, with increasing chip size, not only signal transmission between the chips but also the speed of signal transmission between devices and between constituent circuits (circuit blocks) within one LSI chip (semiconductor integrated circuit device) is becoming a major limiting factor in chip performance.
On the other hand, if the speed of signal transmission between LSI chips is to be extremely increased, for example, it is required that signal receiving circuits be made to operate with correct timing to the signals, and techniques such as DLL (Delay Locked Loop) and PLL (Phase Locked Loop) have been known for addressing this requirement.
In addition, the need has arisen for high-speed signal transmission between LSI chips, for example, between a DRAM and a processor (logic circuit), or between a plurality of devices or circuit blocks within one LSI chip. There is, therefore, a need for a timing signal generating circuit that can generate with simple circuitry and with high accuracy a plurality of timing signals, having prescribed phase differences, synchronous with a reference clock.
Furthermore, with increasing operating speeds of LSIs, there is also a need for a signal transmission system that can perform large-capacity signal transmission at high speed between LSIs and between apparatuses constructed with a plurality of LSIs.
The prior art and the problems associated with the prior art will be described in detail later with reference to drawings.